2-line bus-port esd-prot ection - flow through design VBUS052CD-FAH vishay semiconductors document number: 81881 for technical questions, contact: esdprotection@vishay.com www.vishay.com rev. 1.2, 19-may-10 1 marking (example only) dot = pin 1 marking y = type code (see table below) xx = date code features ? compact llp1713-7l package ? low package height < 0.6 mm ? 2-line esd-protection ? low leakage current i r < 0.1 a ? low load capacitance c d = 0.8 pf ? ideal for high sp eed data line like - hdmi, displayport, esata - usb, 1394/firewire ? esd-protection acc. iec 61000-4-2 15 kv contact discharge 15 kv air discharge ? soldering can be checked by standard vision inspection. no x-ray necessary ? e4 - precious metal (e.g. ag, au, nipd, nipdau) (no sn) ? compliant to rohs directive 2002/95/ec and in accordance to weee 2002/96/ec 21323 21325 7 654 123 gnd nc nc gnd d + d - yxx 20719 ordering information device name ordering code taped units per reel (8 mm tape on 7" reel) minimum order quantity VBUS052CD-FAH VBUS052CD-FAH- g s08 3000 15 000 package data device name package name type code weight molding compound flammability rating moisture sensitivity level soldering conditions VBUS052CD-FAH llp1713-7l g 3.7 mg ul 94 v-0 msl level 1 (according j-std-020) 260 c/10 s at terminals absolute maximum ratings parameter test conditions symbol value unit peak pulse current acc. iec 61000-4-5; t p = 8/20 s; single shot i ppm 3.5 a peak pulse power acc. iec 61000-4-5; t p = 8/20 s; single shot p pp 63 w esd immunity contact discharge acc. iec 61000-4-2; 10 pulses v esd 15 kv air discharge acc. iec 61000-4-2; 10 pulses v esd 15 kv operating temperature junction temperature t j - 40 to + 125 c storage temperature t st g - 55 to + 150 c ** please see document vishay material category policy: www.vishay.com/doc?99902
VBUS052CD-FAH vishay semiconductors 2-line bus-port esd-protection - flow through design www.vishay.com for technical questions, contact: esdprotection@vishay.com document number: 81881 2 rev. 1.2, 19-may-10 note ? ratings at 25 c, ambient temperature unless otherwise specified application note the VBUS052CD-FAH is a two-line esd-protection device with the characteristic of a z-diode with a high esd immunity and a very low capacitance which makes it usable for high frequency applications like usb2.0 or hdmi. with the VBUS052CD-FAH two high speed data lines can be protected against transient voltage signals like esd (electro static discharge). connected to the data line (pin 1 and pin 2) and to ground (pin 3) negative transients will be clamped close below the ground level while positive transients will be clamped close above the 5 v workin g range. the clamping behaviour of the VBUS052CD-FAH is bidirectional but asymmetrical ( bias ) and so it offers the best protectio n for applications running up to 5 v. pin configuration: ? pin 3, 4 and 7 are internally shorted and have to be connected to ground ? pin 1 and 2 are the inputs for the data lines d + and d - ? pin 5 and 6 are not connected internally flow through design modern digital transmission lines can be cl ocked up to 480 mbit/s (usb2.0) or 1.65 g bit/s (hdmi). at such high data rates the transmission lines like cables or th e line traces on the pcbs have to be very homogeneous regarding their surge impedance. th is requires well defined trace dimensions as trac e width and distance which have to be calculated depending on the requeste d surge impedance (e.g. 50 ) and the pcb material and layer dimensions. any device connected to the data lines - like esd-protection de vices - have to be connected with minimal changes in these trace dimensions and distances. with the package in the so called flow through design this is possible. the lines are running straight along the pcb while th e VBUS052CD-FAH is placed on top without any vias or loops. electrical characteristics VBUS052CD-FAH (pin 1 or 2 to pin 3) parameter test conditions/re marks symbol min. typ. max. unit protection paths number of li ne which can be protected n lines --2lines reverse working voltage at i r = 0.1 a v rwm 5--v reverse current at v r = v rwm = 5 v i r - < 0.01 0.1 a reverse breakdown voltage at i r = 1 ma v br 6.9 7.9 8.7 v clamping voltage at i pp = 1 a; acc. iec 61000-4-5 v c -1012v at i pp = 3.5 a; acc. iec 61000-4-5 v c -1518v forward clamping voltage at i f = 1 a; acc. iec 61000-4-5 v f -1.92.4v at i f = 3.5 a; acc. iec 61000-4-5 v f -45v line capacitance at v r = 0 v; f = 1 mhz c d -0.81pf 21325 7 654 123 gnd nc nc gnd d + d - 21327 123 6 5 4 7 matched pair gnd d + d - i/o port connector u s b/hdmi interface d + d -
VBUS052CD-FAH 2-line bus-port esd-protection - flow through design vishay semiconductors document number: 81881 for technical questions, contact: esdprotection@vishay.com www.vishay.com rev. 1.2, 19-may-10 3 typical characteristics (t amb = 25 c, unless otherwise specified) fig. 1 - esd discharge current wave form acc. iec 61000-4-2 (330 /150 pf) fig. 2 - 8/20 s peak pulse current wave form acc. iec 61000-4-5 fig. 3 - typical capacitance c d vs. reverse voltage v r fig. 4 - typical forward current i f vs. forward voltage v f fig. 5 - typical reverse voltage v r vs. reverse current i r fig. 6 - typical peak clamping voltage v c vs. peak pulse current i pp 0 % 20 % 40 % 60 % 8 0 % 100 % 120 % - 10 0 10 20 30 40 50 60 70 8 0 90 100 time (ns) discharge c u rrent i esd rise time = 0.7 ns to 1 ns 53 % 27 % 20557 0 % 20 % 40 % 60 % 8 0 % 100 % 010203040 time (s) i ppm 20 s to 50 % 8 s to 100 % 2054 8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 0.9 1.0 012345 f = 1 mhz pin 2 at 3 v pin 2 at 0 v pin 2 at 5 v v r at pin 1 (v) c d (pf) 214 8 0 0.001 0.01 0.1 1 10 100 0.5 0.6 0.7 0. 8 0.9 1 1.1 pin 3 to pin 1 or 2 2147 8 v f (v) i f (ma) 0 1 2 3 4 5 6 7 8 9 0.01 0.1 1 10 100 1000 10 000 pin 1 or 2 to pin 3 21479 i r (a) v r (v) 0 2 4 6 8 10 12 14 16 1 8 012345 meas u red acc. iec 61000-4-5 ( 8 /20s - w a v e form) v c pin 1 or 2 to pin 3 pin 3 to pin 1 or 2 214 8 1 i pp (a) v c (v)
VBUS052CD-FAH vishay semiconductors 2-line bus-port esd-protection - flow through design www.vishay.com for technical questions, contact: esdprotection@vishay.com document number: 81881 4 rev. 1.2, 19-may-10 fig. 7 - typical clamping performance at + 8 kv contact discharge (acc. iec 61000-4-2) fig. 8 - typical clamping performance at - 8 kv contact discharge (acc. iec 61000-4-2) fig. 9 - typical peak clamping voltage at esd contact discharge (acc. iec 61000-4-2) - 40 - 20 0 20 40 60 8 0 100 120 - 10 0 10 20 30 40 50 60 70 8 090 acc. iec 61000-4-2 + 8 kv contact discharge t (ns) v c-esd (v) 2152 8 - 1 8 0 - 160 - 140 - 120 - 100 - 8 0 - 60 - 40 - 20 0 20 - 10 0 10 20 30 40 50 60 70 8 090 t (ns) v c-esd (v) 21529 acc. iec 61000-4-2 - 8 kv contact discharge - 300 - 250 - 200 - 150 - 100 - 50 0 50 100 150 200 0 5 10 15 20 v esd (kv) v c-esd (v) 21530 acc. iec 61000-4-2 contact discharge v c-esd positi v e discharge n egati v e discharge
VBUS052CD-FAH 2-line bus-port esd-protection - flow through design vishay semiconductors document number: 81881 for technical questions, contact: esdprotection@vishay.com www.vishay.com rev. 1.2, 19-may-10 5 package dimensions in millimeters (inches): llp1713-7l solder resist mask solder pad 0.5 (0.020) 0.25 (0.010) 1 (0.039) 0.15 (0.006) 0.37 (0.015) 0.22 (0.009) pin 1 marking 0.05 (0.002) 0 (0.000) 0.152 (0.006) ref. 1 (0.039) ref. 0.5 (0.020) b sc 0.2 8 (0.011) 0.22 (0.009) 1.4 (0.055) 1.3 (0.051) 0.6 (0.024) 0.5 (0.020) 1.75 (0.069) 1.65 (0.065) 0.25 (0.010) 0.19 (0.007) 0.4 (0.016) 0.4 (0.016) 21329 created - date: 15. april 200 8 doc u ment no.:s 8 -v-3906.04-00 8 (4) re v . 2 - date: 09. sep. 200 8 foot print recommendation:
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